PSoC® 6 MCU is a high-performance, ultra-low-power and secure MCU platform, purpose-built for IoT applications. Based on the PSoC 6 MCU platform, this product line is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.

Features :

32-bit Dual CPU Subsystem

• 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU)
• 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU
• User-selectable core logic operation at either 1.1 V or 0.9 V
• Active CPU current slope with 1.1-V core operation
  • Cortex-M4: 40 µA/MHz
  • Cortex-M0+: 20 µA/MHz
• Active CPU current slope with 0.9-V core operation
  • Cortex-M4: 22 µA/MHz
  • Cortex-M0+: 15 µA/MHz
• Three DMA controllers

Memory Subsystem

• 512-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU.
• 256-KB SRAM with programmable power control and retention granularity
• One-time-programmable (OTP) 1-Kb eFuse array

Low-Power 1.7-V to 3.6-V Operation

• Six power modes for fine-grained power management
• Deep Sleep mode current of 7 µA with 64-KB SRAM retention
• On-chip DC-DC buck converter, <1 µA quiescent current
• Backup domain with 64 bytes of memory and real-time clock

Segment LCD Drive

• Supports up to 63 segments and up to 8 commons.
• Operates in system Deep Sleep mode

Serial Communication

• Seven run-time configurable serial communication blocks (SCBs)
  • Six SCBs: configurable as SPI, I2C, or UART
  • One Deep Sleep SCB: configurable as SPI or I2C
• USB Full-Speed device interface
• One SD Host Controller/eMMC/SD controller
• One CAN FD block

Timing and Pulse-Width Modulation

• Twelve timer/counter/pulse-width modulators (TCPWMs)
• Center-aligned, edge, and pseudo-random modes
• Comparator-based triggering of Kill signals

Programmable Analog

• 12-bit 2-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging
• Two low-power comparators available in system Deep Sleep and Hibernate modes
• Built-in temperature sensor connected to ADC

Up to 64 Programmable GPIOs

• Two Smart I/O™ ports (8 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep
• Programmable drive modes, strengths, and slew rates
• Two overvoltage-tolerant (OVT) pins

IDE :

XMC